The present invention relates to a negative overvoltage protection circuit for insulated vertical PNP transistors.
As known, insulated vertical PNP transistors, by virtue of their relative advantages with respect to lateral PNP transistors (i.e. higher gain, higher cutoff frequency, smaller bulk) are preferred over the latter in applications. A low-drop control circuit is quite often used with said insulated vertical transistors (low-drop configuration), as shown in FIG. 1. As can be seen, the PNP transistor, indicated by Q.sub.P, has an emitter which defines the input terminal which receives the input voltage V.sub.IN, a collector which defines the output terminal on which the voltage V.sub.OUT is present and a base which is connected to the collector of an NPN transistor Q.sub.N the emitter whereof is connected to the ground and the base whereof is connected, by means of a current source I.sub.g, to the input terminal or to a reference voltage source.
This (circuital) configuration is used for example in low-drop regulators, in driving devices which operate as switches for inductive loads, such as relays ("high-side drivers") or in controlled switches.
In all these applications, the need often arises to be able to connect the output V.sub.OUT to the ground or to a more negative voltage of the substrate. However, this entails problems due to the physical execution of the insulated vertical PNP transistor. Said transistor is in fact executed in the manner illustrated in FIG. 2, wherein the reference numeral 1 indicates the P-type substrate which is connected to the ground, the reference numeral 2 indicates the N-type epitaxial layer, the reference numeral 3 indicates the junction insulation ring which surrounds the portion of epitaxial layer, indicated by 2', which internally accommodates the PNP transistor. In particular, the N.sup.+ -type buried layer 4, the P-type collector region 5, the N-type base region 6 (formed by a further portion of the epitaxial layer and provided with an N.sup.+ -type enhanced region 7 to provide the contact) and the P-type emitter region 8 are defined within said portion 2'. The figure also indicates the collector contact C, the base contact B and the emitter contact E, as well as (in broken lines) the parasite structures constituted by the substrate diode D.sub.s which is formed between the insulation 3 and the N.sup.+ -type enhanced region 9 (on which the contact A is formed), by the Zener diode D.sub.z which is formed between the collector region 5 and the buried layer 4, as well as by the diode D which is formed between the buried layer 4 and the substrate 1, and is therefore anti-series connected to D.sub.z .
If the contact A (and therefore the ring formed by the portion 2' of the epitaxial layer) is short-circuited with the collector C, as normally occurs, the substrate diode D.sub.s starts to conduct as soon as the voltage on the collector C drops to approximately -0.7 V with respect to the voltage of the substrate (ground).
In order to solve this problem, it is currently preferred to leave the portion 2' floating, i.e. with the terminal A not connected. In this condition, the negative voltage which the output can withstand is related to the breakdown of the Zener diode plus the drop across the diode D (see FIG. 1).
However, even this solution is not free from disadvantages, which are related to the maximum voltage which the vertical PNP transistor can withstand between the emitter and the collector. To clarify this problem, consider for example an insulated vertical PNP transistor diffused with a process for which BV.sub.CEO =20 V, BV.sub.CBO =30 V and BV.sub.Dz =15 V. In this case, if the input voltage V.sub.IN =10 V, the output voltage V.sub.OUT cannot drop below -10 V, otherwise the transistor Q.sub.P breaks down for BV.sub.CEO. Keeping the PNP transistor on when its collector reaches a voltage which is lower than the ground can further more entail several problems.